\doxysubsubsubsection{DMA mode }
\hypertarget{group___d_m_a__mode}{}\label{group___d_m_a__mode}\index{DMA mode@{DMA mode}}


DMA mode.  


\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___d_m_a__mode_ga04941acfbbdefc53e1e08133cffa3b8a}{DMA\+\_\+\+NORMAL}}~((uint32\+\_\+t)0x00000000U)
\item 
\#define \mbox{\hyperlink{group___d_m_a__mode_ga4c4f425cba13edffb3c831c036c91e01}{DMA\+\_\+\+CIRCULAR}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadc248dbc519cc580621cdadcdd8741fb}{DMA\+\_\+\+Sx\+CR\+\_\+\+CIRC}})
\item 
\#define \mbox{\hyperlink{group___d_m_a__mode_ga7974ee645c8e275a2297cf37eec9e022}{DMA\+\_\+\+PFCTRL}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11f412d256043bec3e01ceef7f2099f2}{DMA\+\_\+\+Sx\+CR\+\_\+\+PFCTRL}})
\item 
\#define \mbox{\hyperlink{group___d_m_a__mode_gaccc83bb7f8aa42b64239afdb65e29fa1}{DMA\+\_\+\+DOUBLE\+\_\+\+BUFFER\+\_\+\+M0}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\+\_\+\+Sx\+CR\+\_\+\+DBM}})
\item 
\#define \mbox{\hyperlink{group___d_m_a__mode_ga10ef5902d35d6226c165e5b72ad6dcc4}{DMA\+\_\+\+DOUBLE\+\_\+\+BUFFER\+\_\+\+M1}}~((uint32\+\_\+t)(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\+\_\+\+Sx\+CR\+\_\+\+DBM}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd36c677ee53f56dc408cd549e64cf7d}{DMA\+\_\+\+Sx\+CR\+\_\+\+CT}}))
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
DMA mode. 



\label{doc-define-members}
\Hypertarget{group___d_m_a__mode_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___d_m_a__mode_ga4c4f425cba13edffb3c831c036c91e01}\index{DMA mode@{DMA mode}!DMA\_CIRCULAR@{DMA\_CIRCULAR}}
\index{DMA\_CIRCULAR@{DMA\_CIRCULAR}!DMA mode@{DMA mode}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_CIRCULAR}{DMA\_CIRCULAR}}
{\footnotesize\ttfamily \label{group___d_m_a__mode_ga4c4f425cba13edffb3c831c036c91e01} 
\#define DMA\+\_\+\+CIRCULAR~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadc248dbc519cc580621cdadcdd8741fb}{DMA\+\_\+\+Sx\+CR\+\_\+\+CIRC}})}

Circular mode \Hypertarget{group___d_m_a__mode_gaccc83bb7f8aa42b64239afdb65e29fa1}\index{DMA mode@{DMA mode}!DMA\_DOUBLE\_BUFFER\_M0@{DMA\_DOUBLE\_BUFFER\_M0}}
\index{DMA\_DOUBLE\_BUFFER\_M0@{DMA\_DOUBLE\_BUFFER\_M0}!DMA mode@{DMA mode}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_DOUBLE\_BUFFER\_M0}{DMA\_DOUBLE\_BUFFER\_M0}}
{\footnotesize\ttfamily \label{group___d_m_a__mode_gaccc83bb7f8aa42b64239afdb65e29fa1} 
\#define DMA\+\_\+\+DOUBLE\+\_\+\+BUFFER\+\_\+\+M0~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\+\_\+\+Sx\+CR\+\_\+\+DBM}})}

Double buffer mode with first target memory M0 \Hypertarget{group___d_m_a__mode_ga10ef5902d35d6226c165e5b72ad6dcc4}\index{DMA mode@{DMA mode}!DMA\_DOUBLE\_BUFFER\_M1@{DMA\_DOUBLE\_BUFFER\_M1}}
\index{DMA\_DOUBLE\_BUFFER\_M1@{DMA\_DOUBLE\_BUFFER\_M1}!DMA mode@{DMA mode}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_DOUBLE\_BUFFER\_M1}{DMA\_DOUBLE\_BUFFER\_M1}}
{\footnotesize\ttfamily \label{group___d_m_a__mode_ga10ef5902d35d6226c165e5b72ad6dcc4} 
\#define DMA\+\_\+\+DOUBLE\+\_\+\+BUFFER\+\_\+\+M1~((uint32\+\_\+t)(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\+\_\+\+Sx\+CR\+\_\+\+DBM}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd36c677ee53f56dc408cd549e64cf7d}{DMA\+\_\+\+Sx\+CR\+\_\+\+CT}}))}

Double buffer mode with first target memory M1 \Hypertarget{group___d_m_a__mode_ga04941acfbbdefc53e1e08133cffa3b8a}\index{DMA mode@{DMA mode}!DMA\_NORMAL@{DMA\_NORMAL}}
\index{DMA\_NORMAL@{DMA\_NORMAL}!DMA mode@{DMA mode}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_NORMAL}{DMA\_NORMAL}}
{\footnotesize\ttfamily \label{group___d_m_a__mode_ga04941acfbbdefc53e1e08133cffa3b8a} 
\#define DMA\+\_\+\+NORMAL~((uint32\+\_\+t)0x00000000U)}

Normal mode \Hypertarget{group___d_m_a__mode_ga7974ee645c8e275a2297cf37eec9e022}\index{DMA mode@{DMA mode}!DMA\_PFCTRL@{DMA\_PFCTRL}}
\index{DMA\_PFCTRL@{DMA\_PFCTRL}!DMA mode@{DMA mode}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_PFCTRL}{DMA\_PFCTRL}}
{\footnotesize\ttfamily \label{group___d_m_a__mode_ga7974ee645c8e275a2297cf37eec9e022} 
\#define DMA\+\_\+\+PFCTRL~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11f412d256043bec3e01ceef7f2099f2}{DMA\+\_\+\+Sx\+CR\+\_\+\+PFCTRL}})}

Peripheral flow control mode 